(1) Field of the Invention
The invention relates to a memory device, and, more particularly, to a method to improve the reading margin in a SRAM device.
(2) Description of the Prior Art
Static memory devices (SRAM) are used in a wide variety of electronics applications. SRAM devices provide a randomly accessible memory array where the data contents can be written and re-written at any time. Further, the SRAM storage cells are constructed such that the static operating current is very low.
Referring now to FIG. 1, an exemplary SRAM memory cell 10 is shown in circuit schematic form. A typical SRAM cell 10 comprises six transistors (6T). A cross-coupled inverter pair N122, P114, N226, and P218 and access transistors N330 and N434 make up the cell 10. The cell is powered by a supply VCC 54. During a write operation, a write data state is set by forcing complimentary voltages (0 and 1) on the bit line (BL) 50 and bit line bar (BLB) 46 lines. Then the access transistors N3 and N4 are turned ON by forcing the word line signal (WL) 48 high. This allows the data state to be forced into the cross-coupled pair. The access transistors are then turned OFF. The positive feedback of the cross-coupled pair will insure that the new data state is maintained.
Typically, the memory cell 10 is replicated many times on the SRAM device to form a large array of SRAM memory cells. Referring now to FIG. 2, a portion of such an array 100 is shown. Four SRAM cells CELL00101, CELL01113, CELL10125, and CELL11137 are arranged in an array. In general, the overall SRAM array 100 may contain millions of such cells. Each SRAM cell comprises the same 6T arrangement as shown in FIG. 1. The cells 101, 113, 125, and 137 are accessed using the word line signals WL0156 and WL1158 and the bit line signals BL0162, BLB0160, BL1166, and BLB1164. Several features should be noted in the prior art memory array. First, the word lines WL0 and WL1 are coupled to more than one cell. For example, WL0156 is coupled to both CELL00101 and CELL01113. Therefore, the access transistors for both cells are turned ON at the same time during a reading or writing event. In general, a larger sub-array of cells would have a common word line. Further, the bit line signals BL0, BLB0, BL1, and BLB1 are coupled to more than one cell. For example, the complimentary bit line signals BLB0160 and BL0162 are coupled to both CELL00101 and CELL10125. These bit line signals can be shared by a large number of cells because only one row of cells, those with the same word line, are accessed at any time. The access transistors for non-selected cells are turned OFF since the word lines for those rows are not asserted. Of particular importance to the present invention is the fact that all of the memory cells 101, 113, 125, and 137 in the memory array 100 are powered by the same power supply VCC 152.
Referring now to FIG. 3, an exemplary SRAM architecture is shown. The entire SRAM array 100 may include millions of cells. The word line decoder 170 controls all of the word line signals WL(0:n) 178 for the array 100 where the array contains a total of n+1 rows of cells. The bit line decoder 174 controls all of the bit line signals, shown as BL(0:m) 182 and implying both BL and BLB compliments, where the array contains a total of m+1 columns of cells. The word line and bit line decoders 170 and 174 respond to the command state (READ or WRITE), the address state, and the data state of the SRAM to assert the correct word line WL(0:n) 178 and to either drive the bit lines BL(0:m) 182 to the correct WRITE state or to READ the stored state of the selected cells. Again, the entire SRAM array is powered by a single supply level VCC 152.
Design rules continue to shrink for high density and high performance SRAM devices. As a result, the operating voltage, VCC, of these devices must be reduced to maintain the thermal stability and reliability and to reduce power consumption. However, as the power supply voltage, VCC, is reduced to below about 1.2 Volts, SRAM cell operation can be adversely affected. In particular, a very low VCC level can cause soft errors. Soft errors occur due to the small VCC level reducing the cell reading margin. In a soft error, a SRAM cell that has correctly maintained the cell state will, nevertheless, be incorrectly read by the sensing circuit due to random effects, such as noise, that cannot be overcome due to insufficient margin. In this case, the benefits of a reduced VCC level described above, are offset by the increase in soft error rate.
Several prior art inventions relate to memory devices. U.S. Pat. No. 6,266,269 B1 to Karp et al discloses a memory device comprising an array of three terminal, nonvolatile memory cells. The word lines of the cells are driven by a circuit powered by the VCC line. U.S. Pat. No. 6,157,558 to Wong describes a content addressable memory cell structure based on an SRAM cell. A mask control circuit is used to ground all mask lines. U.S. Pat. No. 5,726,932 to Lee et al illustrates a SRAM cell structure. U.S. Pat. No. 5,757,696 to Matsuo et al teaches a nonvolatile memory cell based on a 6T structure including two floating gate devices.